1. Technical Field
The present disclosure relates to a method of forming a gate oxide layer and a method of forming a gate electrode having the same. More particularly, the present disclosure relates to a method of forming a gate oxide layer that includes an oxynitride layer that is formed using a nitride layer pattern as an etching mask and a method of forming a gate electrode having the gate oxide layer.
2. Discussion of the Related Art
A semiconductor memory device is classified into a random access memory (RAM) device and a read only memory (ROM) device. The RAM device such as a dynamic random access memory (DRAM) device and a static random access memory (SRAM) device is a volatile memory device. Data is exhausted from the volatile memory device with the lapse of time. Data is, however, rapidly inputted/outputted into/from the volatile memory device. On the contrary, when data is inputted into the ROM device, the data is constantly maintained in the ROM device. Data is, however, slowly inputted/outputted into/from the ROM device.
Further, to meet consumer demand, a system-on-chip device has been manufactured. The system-on-chip device has a single chip in which various semiconductor devices are integrated. For example, the system-on-chip device includes a merged DRAM and logic (MDL) device in which a DRAM region and a logic region are merged, or a merged flash and logic (MFL) device in which a flash memory region and a logic region are merged.
Particularly, the MDL device may have a compact size, a low power consumption, a rapid operation speed, a high efficiency and low electromagnetic interference noise since the DRAM region and the logic region are merged in the single chip. A scale of a semiconductor device in the MDL device is greatly reduced such that a short channel effect is frequently generated in a deep-submicron metal oxide semiconductor (MOS) transistor. To suppress the short channel effect, a dual gate electrode having a surface channel structure and a low threshold voltage is used.
Since a high voltage is applied to the DRAM device, a gate oxide layer having a relatively thick thickness may be employed in the DRAM device. On the contrary, since the logic device operates rapidly, a gate oxide layer having a relatively thin thickness may be employed in the logic device. Accordingly, to manufacture a semiconductor device that operates rapidly with application of a high voltage, the dual gate structure that includes a gate oxide layer having different thicknesses should be employed in the semiconductor device.
In a known method of forming a gate oxide layer having different thicknesses, a silicon nitride layer is formed on a substrate having a first gate oxide layer. The gate oxide layer is etched using the silicon nitride layer as an etching mask to expose a surface of the substrate. A second gate oxide layer is formed on the exposed surface of the substrate.
In a gate electrode including a dual gate oxide layer, a gate oxide layer in a P-type metal oxide semiconductor (P-MOS) transistor of a substrate has a thickness of below about 50 Å. A P-type impurity such as boron (B) or boron trifluoride (BF3) is implanted into a silicon layer. The silicon layer is annealed to form a polysilicon layer.
However, the P-type impurity may infiltrate into a channel region through the gate oxide layer having a thickness of below about 50 Å so that a depletion effect of a poly gate and a fluctuation of a threshold voltage may occur in the gate electrode.
As a result, it is difficult to control the threshold voltage of the gate electrode, thereby deteriorating the characteristics of the P-MOS transistor. Particularly, the threshold voltage fluctuation is generated from penetrating boron into the channel region of the P-MOS transistor.
FIGS. 1A to 1F are cross-sectional views illustrating a conventional method of forming a dual gate electrode including a dual gate oxide layer. In FIGS. 1A to 1F, a first region ‘A’ represents an N-type metal oxide semiconductor (N-MOS) transistor region and a second region ‘B’ represents a P-MOS transistor region.
Referring to FIGS. 1A and 1B, a shallow trench isolation (STI) structure 8 is formed at an upper portion of a substrate 10 to divide the substrate 10 into the first and second regions A and B. The substrate 10 is thermally oxidized to form a first gate oxide layer 12 on the substrate 10. A nitride layer 14 is formed on the first oxide layer 12.
A photoresist pattern 16 is formed on the nitride layer 14 in the first region A. The nitride layer 14 is etched using the photoresist pattern 16 as an etching mask to form a nitride layer pattern 14a positioned in the first region A.
Referring to FIGS. 1C and 1D, the first gate oxide layer 12 is etched using the nitride layer pattern 14a as an etching mask to form a first gate oxide layer pattern 12a positioned in the first region A.
The photoresist pattern 16 is then removed by an ashing process and a stripping process.
A second gate oxide layer 18 is formed in the second region B. For example, the second gate oxide layer 18 is formed via a thermal oxidation process or a local oxidation of silicon (LOCOS) process. The second gate oxide layer 18 has a thickness of about 50 Å. The nitride pattern 14a is then removed by a wet etching process.
Referring to FIGS. 1E and 1F, an oxynitride layer 20 having a predetermined thickness is formed on the first gate oxide layer pattern 12a and the second gate oxide layer 18. A polysilicon layer 22 is then formed on the oxynitride layer 20.
The polysilicon layer 22, the oxynitride layer 20 and the gate oxide layers 12a and 18 are subsequently etched using an etching mask (not shown) to form a first gate electrode 30a in the first region A and a second gate electrode 30b in the second region B. Here, the first gate electrode 30a includes a first gate oxide layer pattern 12b, an oxynitride layer pattern 20a formed on the first gate oxide layer pattern 12b, and a polysilicon layer pattern 22a formed on the oxynitride layer pattern 20a. The second gate electrode 30b includes a second gate oxide layer pattern 18a, an oxynitride layer pattern 20a formed on the second gate oxide layer pattern 18a, and a polysilicon layer pattern 22a formed on the oxynitride layer pattern 20a. 
As described above, the first gate electrode 30a includes the oxynitride layer pattern 20a. Nitrogen having positive charge increases in the first gate electrode 30a due to the oxynitride layer pattern 20a so that a threshold voltage of an N-MOS transistor may be reduced.
To prevent the reduction of the threshold voltage, boron ions are additionally implanted into a channel region after the first gate oxide layer 12 is formed. However, a static refresh property of a transistor may be deteriorated in proportion to an amount of the implanted boron ions, thereby slowing the operation of a semiconductor device.